1. Field of the Invention
The present invention relates to a hitless switching system. More particularly, the present invention relates to a hitless switching system for switching between signals transmitted over a plurality of routes in a synchronous digital transmission network including a plurality of nodes that have multiplexing/demultiplexing capability or cross connect capability.
2. Description of the Related Art
For realizing hitless switching, a signal is branched into two signals in the sending side, and the branched signals are sent over two different routes. Branched signals are the same. Then, in the receiving side, one signal is switched to another signal within one bit after aligning phases between the signals.
FIG. 1 shows a block diagram of a transmission system for explaining a conventional hitless switching technology. The system shown in FIG. 1 includes a sending side apparatus and a receiving side apparatus. The sending side apparatus includes an indicator providing part 11, a branch part 12, a first sending interface 13, a second sending interface 14. The receiving side apparatus includes a first receiving interface 15, a second receiving interface 16, a first elastic store memory 17, a second elastic store memory 18, a phase control part 19, and a selector 20. The indicator providing part 11 receives a signal 101 to be switched with no bit error, and a signal 102 that is switched with no bit error is output from the selector 20.
The signal 101 is provided with an indicator used for phase control in the indicator providing part 11. Then, the signal 101 is input into the branch part 12. After that, the signal 101 is branched into the first sending interface 13 and the second sending interface 14. Branched signals are the same. According to this process, sending data is sent to different two routes.
The signal input into the first receiving interface 15 is stored in the first elastic store memory 17. The signal input into the second receiving interface 16 is stored in the second elastic store memory 18.
Phases for reading the signals stored in the first elastic store memory 17 and the second elastic store memory 18 are aligned by the phase control part 19. Then, the signals are received by the selector 20. The selector 20 performs switching within one bit. In the switching, it is decided whether the selector 20 receives a signal from the first elastic store memory 17 or receives a signal from the second elastic store memory 18.
According to this process, hitless switching is realized between signals transmitted over different two routes.
The phase aligning between signals transmitted over different two routes are performed in the following way. The signals are temporarily stored in the elastic store memories. Then, phase difference between the signals is detected by using a specific pattern (indicator) that has been inserted into J1 byte multi-frame or H4 byte multi-frame in each signal at the sending side, wherein each of the J1 byte multi-frame and the H4 byte multi-frame exists in POH in synchronous digital hierarchy defined in ITU-T G.707. By detecting the phase difference, the phases of the signals are aligned for reading from the elastic store memories.
As a technology relating to aligning phases, there is a virtual concatenation technology. In the virtual concatenation, an original signal is divided into a plurality of virtual concatenation signals in the sending side. Then, phases are aligned between signals that are transmitted over the same route or over different routes. After that, the original signal is restored.
FIG. 2 shows a block diagram of a transmission system for explaining the virtual concatenation technology. The system shown in FIG. 2 includes a sending side apparatus and a receiving side apparatus. The sending side apparatus includes a distributing part 31, indicator providing parts 321˜32n, sending interfaces 331˜33n. The receiving side apparatus includes receiving interfaces 341˜34n, elastic store memories 351˜35n, a phase control part 36, and a restoring part 37. The distributing part 31 receives a signal 201 to which virtual concatenation is to be applied. The signal 201 is divided and transmitted. Then, a restored signal 202 is output from the restoring part 37.
The signal 201 is divided into a plurality of virtual concatenation signals in the distributing part 31. Then, an indicator used for phase control is provided to each virtual concatenation signal in the indicator providing parts 321˜32n. After that, the virtual concatenation signals are input into the sending interfaces 331˜33n so as to be transmitted over the same route or different routes.
The virtual concatenation signals received by the receiving interfaces 341˜34n are stored in the elastic store memories 351˜35n.
Phases for reading the virtual concatenation signals stored in the elastic store memories 351˜35n are aligned by the phase control part 36. Then, the virtual concatenation signals are input into the restoring part 37 so that the original signal is restored.
According to this process, virtual concatenation transmission is realized by dividing and restoring the original signal.
The phase aligning between the virtual concatenation signals is performed in the following way. The virtual concatenation signals which are transmitted over the same route or the different routes are temporarily stored in the elastic store memories. Then, phase difference between signals are detected by using a specific pattern (indicator) that has been inserted, at the sending side, into the H4 byte multi-frame in POH of each signal, wherein the H4 byte multi-frame is defined in ITU-T G.707. By detecting the phase difference, the phases of the signals are aligned when reading from the elastic store memories.
In the conventional hitless switching, the size of the original signal to be switched with no bit error is VC-3 (50 Mbit/s), VC-4 (150 Mbit/s) or VC-4-Xc (150×X Mbit/s (X=4, 16, 64, 256)) that is contiguous concatenation that are defined in ITU-T G.707. However, hitless switching for signals of intermediate bandwidth other than VC-3, VC-4 and VC-4-Xc (X=4, 16, 64, 256) has not been realized, so that efficient use of transmission bandwidth has not been realized.
In the conventional hitless switching, if the J1 byte multi-frame is used for detecting phase difference between signals transmitted over different two routes, there is a problem since the J1 byte is defined as a path trace byte used for uniquely detecting a path in the synchronous digital hierarchy in ITU-T G.707. Thus, if hitless switching is performed by using the J1 byte, the path trace can not be realized, so that the hitless switching and the path trace can not be compatible.
Hypothetically, by connecting the conventional hitless switching and virtual concatenation serially, hitless switching for intermediate bandwidth other than VC-3, VC-4, VC-4-Xc (X=4, 16, 64, 256) can be realized. However, in this case, it is necessary to provide a part for detecting phase difference for hitless switching and a part for detecting phase difference for virtual concatenation, in addition, it is necessary to provide elastic store memories for hitless switching and elastic store memories for virtual concatenation. There is a problem in that the configuration of the system becomes complicated and delay increases.
Further in this case, if the H4 byte multi-frame in POH is used for detecting the phase difference, there is a problem in that the H4 byte multi-frame used for hitless switching overwrites the H4 byte multi-frame used for virtual concatenation since the H4 byte is defined as a byte used for detecting phase difference for realizing virtual concatenation. Therefore, in this case, the original signal can not be restored from the divided virtual concatenation signals, so that the hitless switching and the virtual concatenation can not be compatible.
In addition, in the case in which conventional hitless switching and virtual concatenation are connected serially, if J1 byte multi-frame is used for detecting phase difference between signals transmitted over two different routes, there is a problem in that path trace can not be performed for virtual concatenation signals since the J1 byte used for hitless switching overwrites the J1 byte used for path trace. Thus, there is a problem in that the hitless switching and path trace can not be compatible.